static inline void arch_spin_lock(arch_spinlock_t *lock)
{
    unsigned long tmp;
    u32 newval;
    arch_spinlock_t lockval;

    prefetchw(&lock->slock);    // 软件预读 &lock->slock，提前读到 cache
  // [jgsun] LL/SC(Load-Link/Store-Conditional)，实现原子操作
    __asm__ __volatile__(
"1:    ldrex    %0, [%3]\n"         // 将 lock->slock 加载到 lockval, monitor 标记为 exclusive
"    add    %1, %0, %4\n"         // 将 lockval + 1, 保存到 newval
"    strex    %2, %1, [%3]\n"     // 将 newval store 到 lock->slock，如 monitor state 仍为 exclusive，
                                       // 则 store 成功，monitor state 变为 open，并置 tmp 为0，否则 store 不成功置 tmp 为非0
                                      // 如果这期间如果有其它处理器 store，monitor state 将为 open
"    teq    %2, #0\n"               // 判断tmp是否为0
"    bne    1b"                       // 如果非0，返回1继续
    : "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
    : "r" (&lock->slock), "I" (1 << TICKET_SHIFT)
    : "cc"); // The "cc" clobber indicates that the assembler code modifies the flags register. 

    while (lockval.tickets.next != lockval.tickets.owner) {
        wfe(); // 如果 lockval 中的 next 不等了 owner
        lockval.tickets.owner = READ_ONCE(lock->tickets.owner);
    }

    smp_mb();
}

#define TICKET_SHIFT    16

typedef struct {
    union {
        u32 slock;
        struct __raw_tickets {
#ifdef __ARMEB__
            u16 next;
            u16 owner;
#else
            u16 owner;
            u16 next;
#endif
        } tickets;
    };
} arch_spinlock_t;

static inline void arch_spin_unlock(arch_spinlock_t *lock)
{
    smp_mb(); //[jgsun]dsb memory barrier
    lock->tickets.owner++; // [jgsun] owner +1 
    dsb_sev(); //[jgsun] 先调用dsb memory barrier，再调用 __asm__(SEV) 唤醒因为 WFE 指令进入 low-power 模式其他处理器
}

static inline void arch_spin_lock(arch_spinlock_t *lock)
{
    unsigned int tmp;
    arch_spinlock_t lockval, newval;

    asm volatile(
    /* Atomically increment the next ticket. */
    ARM64_LSE_ATOMIC_INSN(
    /* LL/SC */
"    prfm    pstl1strm, %3\n"
"1:    ldaxr    %w0, %3\n"
"    add    %w1, %w0, %w5\n"
"    stxr    %w2, %w1, %3\n"
"    cbnz    %w2, 1b\n",
    /* LSE atomics */
"    mov    %w2, %w5\n"
"    ldadda    %w2, %w0, %3\n"
    __nops(3)
    )

    /* Did we get the lock? */
"    eor    %w1, %w0, %w0, ror #16\n"
"    cbz    %w1, 3f\n"
    /*
     * No: spin on the owner. Send a local event to avoid missing an
     * unlock before the exclusive load.
     */
"    sevl\n"
"2:    wfe\n"
"    ldaxrh    %w2, %4\n"
"    eor    %w1, %w2, %w0, lsr #16\n"
"    cbnz    %w1, 2b\n"
    /* We got the lock. Critical section starts here. */
"3:"
    : "=&r" (lockval), "=&r" (newval), "=&r" (tmp), "+Q" (*lock)
    : "Q" (lock->owner), "I" (1 << TICKET_SHIFT) //Q: A memory address which uses a single base register with no offset
    : "memory");
}

#define TICKET_SHIFT    16

typedef struct {
#ifdef __AARCH64EB__
    u16 next;
    u16 owner;
#else
    u16 owner;
    u16 next;
#endif
} __aligned(4) arch_spinlock_t;

static inline void arch_spin_unlock(arch_spinlock_t *lock)
{
    unsigned long tmp;

    asm volatile(ARM64_LSE_ATOMIC_INSN(
    /* LL/SC */
    "    ldrh    %w1, %0\n"
    "    add    %w1, %w1, #1\n"
    "    stlrh    %w1, %0",
    /* LSE atomics */
    "    mov    %w1, #1\n"
    "    staddlh    %w1, %0\n"
    __nops(1))
    : "=Q" (lock->owner), "=&r" (tmp)
    :
    : "memory");
}